1. Field of the Invention
The present invention relates to a bank controller that controls data communication between banks of a synchronous DRAM and associated FIFO memories, an information processing device and an imaging device having the bank controller, and a control method therefor, and particularly to an improvement of the method of determining the order of priorities of the FIFO memories.
2. Description of the Background Art
Conventionally known methods of performing data communication between a device and memory without through the MPU (Micro Processing Unit) include the DMA (Direct Memory Access) transfer technique, for example. Information processing devices that can implement the DMA transfer scheme are also conventionally known.
Devices involved in a DMA transfer system are assigned numbers (hereinafter referred to also as “DMA channels”) so that the devices can be uniquely identified. In the DMA transfer, data is transferred directly between the memory and a device designated with the DMA channel. When a plurality of devices issue transfer requests to the DMA controller, the DMA controller gives priority for data transfer to a device having a smaller DMA channel number.
Synchronous DRAM (SDRAM: Synchronous Dynamic Random Access Memory) is divided into a plurality of banks, and it is known that each bank is capable of performing data transfer independently of other banks. For example, even when one bank is being precharged, another bank can perform data transfer with a device.
“Precharging” is an operation that is performed to prevent loss of stored data (information) after the data is read out. Data read/write operation cannot be applied to a bank being precharged.
However, if a device that is associated with the bank being precharged is given the high priority, the data transfer operation by the associated device is made to wait until the precharging operation of the bank is completed. Then, the bus that electrically connects the device and the synchronous DRAM is continuously occupied despite the absence of data transfer. This lowers the data transfer efficiency of the entire information processing device.